Along with the rapid development of the electronic industries, the present electronic products are developed towards multi-function and high performance. To meet requirements of semiconductor packages for high integration and miniaturization, package substrates for carrying semiconductor chips have been developed from single layer boards to multi-layer boards. Meanwhile, interlayer connection techniques have been used to increase available circuit layout area in a limited space, thereby meeting requirements of high-density integrated circuits.
The present package substrates for carrying semiconductor chips comprise wire bonding package substrates, chip scale package (CSP) substrates, flip chip ball grid array (FCBGA) package substrates and so on. FIG. 1 exemplifies a conventional flip-chip package substrate. As shown in FIG. 1, a package substrate 11 is provided, which comprises a first surface 11a for chip mounting and a second surface 11b for solder ball attachment. A plurality of first electrical connecting pads 111 to be electrically connected with a semiconductor chip 12 are formed on the first surface 11a, and a plurality of first conductive elements 13a made of solder material are formed on surface of the first electrical connecting pads 111. Further, a plurality of second electrical connecting pads 112 to be electrically connected with other electronic device such as a printed circuit board are formed on the second surface 11b, and a plurality of second conductive elements 13b made of solder material are formed on surface of the second electrical connecting pads 112. The semiconductor chip 12 has a plurality of electrode pads 121. Metal bumps 14 are formed on the surface of each of the electrode pads 121 in a flip-chip manner and corresponding in position to the first conductive elements 13a of the package substrate 11. Then at a reflow temperature capable of melting the first conductive elements 13a, the first conductive elements 13a are reflowed to the corresponding metal bumps 14, thereby electrically connecting the semiconductor chip 12 to the package substrate 11.
However, as the contact area between the second electrical connecting pads 112 on the second surface 11b of the package substrate 11 and the corresponding second conductive elements 13b is only limited to the exposed area of the second electrical connecting pads 112, the bonding force between the second conductive elements 13b and the second electrical connecting pads 112 can be poor due to insufficient contact area therebetween, and accordingly the second conductive elements 13b can easily detach from the second electrical connecting pads 112. For example, if the pitch between the second electrical connecting pads 112 is decreased from 800 μm to 400 μm, and the diameter of each of the openings for the second electrical connecting pads 112 is decreased from 500 μm to 250 μm, the contact area will be decreased to one-fourth of the initial contact area, which thus seriously reduces the bonding force between the conductive elements and the electrical connecting pads.
FIGS. 2A to 2E are diagrams showing a conventional method for increasing the contact area between the conductive elements and the electrical connecting pads on the solder ball disposing surface of a package substrate. As shown in FIG. 2A, the solder ball disposing surface of the package substrate 20 is formed with electrical connecting pads 201. An insulative protection layer 21 is formed on the solder ball disposing surface and the electrical connecting pads 201, and a plurality of openings 210 is formed in the insulative protection layer 21 for exposing a part of the surface of the electrical connecting pads 201. As shown in FIG. 2B, a conductive layer 22 is formed on the insulative protection layer 21 and the exposed surface of the electrical connecting pads 201. As shown in FIG. 2C, a resist layer 23 is formed on the conductive layer 22, and a plurality of ring-shaped openings 230 is formed in the resist layer 23 by exposure and development so as to expose the conductive layer 22 on the electrical connecting pads 201 around the openings 210 of the insulative protection layer 21. As shown in FIG. 2D, by using the conductive layer 22 as a current conductive path for electroplating, flanges 24 are formed in the ring-shaped openings 230, the flanges 24 being attached to periphery of the openings 210 of the insulative protection layer 21. Finally, the resist layer 23 and the conductive layer 22 covered by the resist layer 23 are removed so as to expose the flanges 24 and a part of the surface of the electrical connecting pads 201.
However, since the conductive layer 22 is left between the flanges 24 and the electrical connecting pads 201, the bonding strength between the flanges 24 and the electrical connecting pads 201 is reduced. In addition, as the formed flanges 24 are attached to the periphery of the openings 210 of the insulative protection layer 21, the present method provides only a limited increase of the contact area for the conductive elements such as solder balls subsequently formed on the electrical connecting pads 201 and the flanges 24. As a result, detaching of the solder balls still can easily occur. Therefore, how to provide a structure capable of increasing the bonding force between solder balls and electrical connecting pads on the solder ball disposing surface of a package substrate so as to avoid detaching of the solder balls from the electrical connecting pads caused by reduced bonding area has become urgent.